The present invention relates to the field of computers and particularly to computers having central processing units (CPU's) that operate in accordance with the IBM ESA/390 architecture and particularly to computers that have software control of hardware interruptions.
In existing computer systems there are two layers of architectures, the outer and the inner layers. The outer layer is the architectural layer which is defined, for example, in a specification such as the Principles of Operation (POO) for the IBM ESA/390. At this layer, an interruption is an unexpected transfer of control. The inner layer mainly implements the interruptions. Many interruptions for a CPU may exist concurrently. Therefore, the inner layer maintains a list of those interruptions that are pending in a register, so they may be processed in the order defined by the outer architecture. The inner layer must be able to set bits in the interruption register as they arise, and also be able to clear the bits as the interruptions are serviced.
Various interruptions can be generated by different modules/functions in a computer system. Different classes of interruptions have been defined at the outer layer in the existing computer systems such as External, I/O, Machine Check, Program, Supervisor Call, and Restart interruptions. An interruption signal/level is used to set an appropriate bit in the interrupt register, related to a specific interruption. Next there is an interrupt mask which only permits the allowed interruptions to be seen by the priority encoder. The priority encoder examines the pending interruptions in order to specify which one has the highest priority and needs to be serviced next. After the interruption is serviced, the appropriate bit in the interrupt register is cleared.
Once a bit associated with an interruption is set, Control Software can not reset it. However, the bit can be reset as a part of a CPU Reset or an IPL (Initial Program Loading) operations, or by hardware after the interruption is serviced.
ESA/390 architecture computers are controlled in part by a Program Status Word (PSW). The program-status word (PSW) includes the instruction address, condition code, and other information used to control instruction sequencing and to determine the state of the computer. The active or controlling PSW is called the current PSW. It governs the program currently being executed.
The CPU has an interruption capability, which permits the CPU to switch rapidly to another program in response to exception conditions and external stimuli. When an interruption occurs, the CPU places the current PSW in an assigned storage location, called the old-PSW location, for the particular class of interruption. The CPU fetches a new PSW from a second assigned storage location. This new PSW determines the next program to be executed. When it has finished processing the interruption, the interrupting program may reload the old PSW, making it again the current PSW, so that the interrupted program can continue.
The status of the CPU can be changed by loading a new PSW or part of a PSW. Control is switched during an interruption of the CPU by storing the current PSW, so as to preserve the status of the CPU, and then loading a new PSW.
A new or modified PSW becomes active (that is, the information introduced into the current PSW assumes control over the CPU) when the interruption or the execution of an instruction that changes the PSW is completed.
A storage key is associated with each 4K-byte block of storage that is available in the configuration. The storage key has the following format. ##STR1## The bit positions in the storage key are allocated as follows: